The initial application of a power supply voltage to a semiconductor device is often referred to as "power-up." During power-up at least one supply voltage rapidly rises (ramps-up) to a full scale power supply voltage. For example, in the case of complementary metal oxide semiconductor (CMOS) logic circuits, a positive power supply voltage (Vcc) ramps up from a low voltage of around zero volts, while a second power supply voltage (Vss) is maintained at zero volts. Once the device is powered-up (i.e., Vcc has reached full scale) it will normally operate as designed. The initial power-up of a semiconductor device can result in some uncertainty in the device operation, however. As just one example, in logic circuits employing MOS devices, as the power supply ramps up, some MOS devices may suffer from sub-threshold leakage, pulling nodes to intermediate voltage levels. These nodes can be driven to unintended full logic levels once the power supply has reached its maximum value. As a result, the potential at various nodes within the device may not be predictable following power-up. Consequently, the device may not operate as designed.
To eliminate uncertainty in the configuration of a semiconductor device following power-up, power-on reset circuits are often used. Such circuits are enabled upon power-up, and guarantee that all circuits within the device are properly configured. As just one example, a power-on reset circuit can generate a power-on reset pulse in response to the initial application of the positive supply voltage. The power-on reset pulse propagates through the device, driving the nodes to predetermined logic levels. Once all the nodes are set, the device will operate as designed.
While it is desirable to have predictable circuit operation on power-up, it is also desirable to provide configurability to a semiconductor device. Configurability enables the operation, architecture or other aspects of a semiconductor device to be altered so that the device is adaptable to a wider range of applications and implementations. As just one example, in the case of nonvolatile memory devices, it is desirable to enable such devices to have configurable architectures in which blocks of the memory can be designated as "boot" blocks, and only be altered under special conditions. Further, different nonvolatile memory architectures may be configured for different programming and/or erase algorithms. Such configuration information may also include redundancy information which can designate how defective memory cells may be replaced by redundant memory cells. It is important that once a semiconductor device has been configured, that the configuration information will not be lost, even in the event the power supply voltages supplied to the device are turned off.
A similar concern is raised by devices having power saving modes in which the power supply is disconnected from portions of the device, or the portions of the device are "powered-down" (e.g., for CMOS devices, all nodes brought down to zero volts). When such devices are "woken" up (i.e., power is returned to the circuits) the circuits must be reset. It desirable that such a wake-up operation should not effect the configuration information initially established upon power-up.
User configuration information can be stored in a semiconductor device in a variety of ways. A few examples include "hard wiring" the device in a certain configuration. Hardwiring can include utilizing a particular "mask" option during the fabrication of the device that guarantees nodes within the device are coupled to one logic state. Configuration information can also be placed into the device by altering active device properties, such as the threshold voltages of selected transistors by an ion implantation, or other fabrication step. The assembly step of a semiconductor device can be used to configure a device by a "bonding option", in which selected bond pads of the device are coupled to a selected power supply pin by bond wires. A common, flexible method of storing user configurability information includes utilizing fuse structures. Fuse structures can include fusible links that are opened either electrically by the application of a relatively large current to the fusible link, or by the application of a laser, which vaporizes a portion of the fusible link. Yet another type of "fuse" is an electronic fuse, which utilizes programmable nonvolatile memory structures, such as floating-gate avalanche injected MOS (FAMOS) devices, or other such structures. Programmable nonvolatile memory structures can be more advantageous because the contents stored within such structures can be altered, allowing a user to custom configure a semiconductor device.
A problem associated with semiconductor devices that utilize configurable information is ensuring that the configuration information is properly provided to the device during power-up. The storage structures providing the configuration information may be sensitive to the power supply levels on power-up, and result in incorrect configuration information being provided to the device. If incorrect configuration is generated on power-up, the device will be not function as desired. As just one example, configuration information can be stored in nonvolatile memory cells, and upon power-up, be coupled to volatile memory cells, such as static or dynamic memory cells. Storing configuration information in volatile memory cells can be advantageous, as such cells can be read at faster speeds and/or require lower operating power. In the event the nonvolatile memory cells are coupled to the volatile memory cells prematurely (i.e., before the nonvolatile memory cells are providing stable data), the volatile memory cells may latch/store an incorrect value. The device will be incorrectly configured after power-up.
It would be desirable to provide a semiconductor device that ensures that proper configuration information is provided to the internal circuits during power-up.